1. Field of the Invention
The present invention relates to a method for adapting the phase relationship between a clock signal provided by a memory control unit (memory controller) and a strobe signal provided by the memory control unit during the acceptance of transmitted write data in a memory circuit. The invention furthermore relates to a memory circuit with which the phase relationship between the clock signal and the strobe signal can be adapted. The invention furthermore relates to a memory control unit which adapts the phase relationship between the clock signal and the strobe signal.
2. Description of the Related Art
Conventional memory circuits are usually driven with the aid of a memory control unit (a so-called memory controller) in order to operate the memory circuits in a specification-conforming manner. For the communication of the memory control unit with one or more memory circuits, in particular dynamic random access memory circuits or DRAM memory circuits, use is generally made of a clock signal for the transmission of the command and address data and also a strobe signal for the transmission of the write data which are to be stored in the memory circuit. When the clock signal and the strobe signal arrive in the memory circuit, the strobe signal and the clock signal must comply with a fixedly predefined phase relationship, which is essentially described by a setup time tDSS and a hold time tDSH for the strobe signal relative to the clock signal, in order to ensure that data to be written are accepted correctly into the memory circuit.
Compliance with said phase relationship is usually achieved through careful adaptation of the interconnect lengths between the memory control unit and the respective memory circuit for the clock signal and the strobe signal and also for the corresponding command and address signals and the data signals. It must be taken into account in this case, however, that the respective signals, under certain circumstances, have different propagation speeds on their respective signal lines, e.g. on account of different loads of the inputs connected thereto, and also by virtue of their different physical properties.
In the case of certain bus arrangements between the memory control unit and the memory circuits of a memory module, equalization of the propagation times is possible only in a very limited frequency band or is no longer possible at all under certain circumstances. Particularly when using a fly-by bus for the transmission of the clock signal and of the command and address data transmitted in a manner synchronized therewith, a non-defined phase offset occurs between the clock signal and strobe signal. The corresponding signal propagation times when using the fly-by bus are usually longer than in the case of the lines for the transmission of the strobe signal and the data signals transmitted in a manner synchronized therewith, which are usually embodied in the form of a point-to-point (P2P) connection between the memory control unit and the memory circuit.
In this regard, the memory control unit usually has a circuit which generates the clock signal and the strobe signal for the memory circuits, it being possible for the temporal relationship of the two signals to be set within certain limits. Such a circuit can be used to set the phase relationship of the two signals upon arrival at the corresponding memory circuit, independently of the relative length of the lines for the clock signal and the strobe signal and the loads present on them.
In order to be able to set the phase relationship of the memory control unit in such a way that the signals arrive at the memory circuit with the desired phase offset or correctly in terms of phase, the memory circuit may be provided with a phase comparator that measures the temporal relationship between the clock signal and the strobe signal. The measured result is transmitted to the memory control unit, which can thereupon correspondingly correct the delay time chosen between the clock signal and the strobe signal. Since the temporal relationship between the clock signal and the strobe signal can only be measured relatively inaccurately with a tenable outlay on circuitry, in particular also owing to the production technology used in the case of memory circuits, it is necessary to take account of large tolerances in the setting of the phase relationship in the memory control unit, so that the maximum operating frequency of the memory circuit is limited.
A further possible disadvantage is that the phase comparator merely determines the phase information between clock signal and strobe signal, but without simulating the actual failure mechanism of the memory circuit in the case of a non-indication-conforming phase relationship between the clock signal and the strobe signal. That is to say that while the clock signal and the strobe signal have hitherto been applied by the memory control unit in such a way that they are present at the respective memory circuit with a defined phase relationship which lies within the values predefined by the indication, provision has not been made hitherto for operating memory circuits outside the limit values predefined by the indication, even if they can be operated without errors beyond the specification-conforming limits.